Memory devices that use resistance materials include resistive RAMs (RRAM), phase change random access memories (PRAM), ferroelectric RAMs (FRAM), magnetic RAMs (MRAM), etc. Dynamic RAMs (DRAM) or flash memory devices store data using stored charge, while some other nonvolatile memory devices store data by using a variation in the resistance of a variable resistance material (RRAM), a variation in the state of a phase change material, such as a chalcogenide alloy (PRAM), a polarization phenomenon of a ferroelectric material (FRAM), or a variation in the resistance of a magnetic tunnel junction film (MTJ film) according to the magnetized state of a ferroelectric material (MRAM), for example.
FIG. 1 is a view illustrating a resistive memory cell. Referring to FIG. 1, a resistive memory cell includes an upper electrode 1, a lower electrode 3, and a variable resistive material 2 interposed therebetween. The resistance level of the variable resistive material is changed according to a voltage applied to the upper and lower electrodes 1 and 3. An example of such a resistive memory cell is disclosed in U.S. Patent Application Publication Nos. 2005-58009 and 2004-27849.
When the resistive memory device is fabricated and a filament-forming voltage having a considerably high level is applied to the resistive memory cells including the variable resistive material 2, filaments 4 are formed in the variable resistive material 2 (see (A) of FIG. 1). The filaments 4 form a current path of a cell current flowing between the upper electrode 1 and the lower electrode 3, After the filaments 4 are formed, a reset voltage may be applied so as to make the variable resistive material 2 be in a reset state (see (B) of FIG. 1) or a set voltage may be applied to make the variable resistive material 2 be in a set state (see (C) of FIG. 1). Here, the reset state means a relatively high-resistance state in which filaments 4a in the variable resistive material 2 are in an open state and can be defined as data “1”, and the set state means a relatively low-resistance state in which filaments 4b in the variable resistive material 2 are in a short state and can be defined as data “0”. Typically, when it is assumed that the filament-forming voltage is Vform, the set voltage is Vset, and the reset voltage is Vreset, the following relationship is established: Vform>Vset>Vreset.
In the resistive memory device according to the related art, the filament-forming voltage having the same level is applied to all of the resistive memory cells. Since the filament-forming voltage may be a relatively high level, the variable resistive material 2 may be partially broken down, or the filaments may be formed to be excessively thick such that transition from the reset state to the set state or transition from the set state to the reset state can become difficult.